• Version 4.0
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• Create Date January 24, 2023
• Last Updated January 24, 2023

HSIP Design Rules - Revision 4

Fan out wafer level packages have emerged across the market in an effort to reduce size and weight of electronics used in portable and wearable applications in the commercial, industrial, and the hi-reliability products space. If it is not a stationary platform, weight and volume reduction are also imperative. For the stationary platforms, size and power are most critical. Integration of multiple complex heterogeneous IC components can only be done if there are a sufficient number of interconnect layers. Additionally, multiple interconnects are needed for transmission line creation and shielding. The i3 Microsystems HSiP technology is an extension of 2.5D/3D FOWL and CSP technologies allowing embedded heterogeneous components, TSV, and multi-layer top and bottom interconnects.